In part 1 we followed the stimulus out of the MAX2871 and through its filter bank. This time we look at the other end of the instrument: the receiver. A VNA has to turn a signal of several gigahertz into numbers a processor can work with, and the obvious question is the one I asked myself when I started studying LibreVNA: why not put an ADC right on the RF signal and sample it? Is there an ADC that can even reach 3.9 GHz?

By the end of this article, you'll understand:

  • What sample rate a 3.9 GHz signal needs, and which real ADC gets there
  • Why that ADC is possible but impractical for an open-hardware VNA
  • How LibreVNA's heterodyne receiver lets a 16-bit, 800 kSps ADC do the job

Why Build Your Own VNA?

Over a career, some instruments are always on the bench: the multimeter, the power supply, the logic analyzer and the Swiss Army knife of electronics, the oscilloscope. Push hard enough and in a couple of years you know every knob on them. The vector network analyzer is different. It is the instrument that lets a manufacturer prove an antenna works across a band, or that a pin has a particular impedance, and most engineers never touch one because of what it costs: from a few thousand dollars for an entry-level unit to well into six figures for the high end.

If I had to define it in one line: a VNA measures the magnitude and phase of a signal, relative to the stimulus it sent, and shows them on a polar plot or a Smith chart. The moment you ask "what is the impedance of my antenna at 4.5 GHz?" is the moment the Smith chart stops being a classroom exercise.

Building (or studying) one forces you past the usual comfort zone of SPI sensors and ready-made modules. You meet op amps in cascade, external ADCs and the signal conditioning that uses their full range, TCXOs and clock fan-out, differential signals, and the question this article is about: at what sample rate, and at what frequency, should the signal be digitized?

The Problem: Getting 3.9 GHz Into a Computer

Let's make it concrete. Say we want to measure the frequency response at the output of a Qorvo QPA9154, a small-cell amplifier rated from 2.3 to 3.8 GHz. To see the edges of its band we sweep a little past it, just like the datasheet plots do, so the highest frequency our receiver has to capture is about 3.9 GHz.

QPA9154 output return loss versus frequency from 2.3 to 3.9 GHz at +105, +25 and -40 °C
Output return loss of the QPA9154, plotted from 2.3 to 3.9 GHz. From the Qorvo QPA9154 datasheet.

The VNA generates a stimulus at one frequency, sends it through the amplifier, and picks off what comes back. That signal is still at the stimulus frequency. Somewhere between the RF connector and the processor, it has to become numbers. There are two ways to get there.

Top: a direct sampling receiver where the DUT output passes through a 3.9 GHz low-pass filter into an 8 GSPS ADC12DJ4000RF, which streams about 96 Gb/s over JESD204C into an FPGA. Bottom: the LibreVNA receiver, where an ADL5801 mixer converts the RF to 62 MHz, an LT5560 mixer converts it to 250 kHz, and a THS4521 drives an MCP33131D ADC at 800 kSps into an XC6SLX9 FPGA.
Two ways to digitize the same signal. LibreVNA part numbers are taken from its KiCad BOM.

Option 1: Sample It Directly

Nyquist Says 7.8 GSPS

The Nyquist criterion says the sample rate must be more than twice the highest frequency in the signal:

fs > 2 × fmax = 2 × 3.9 GHz = 7.8 GSPS

Above about 1 GSPS you are firmly in "high-speed ADC" territory, and 7.8 GSPS is near the top of what you can buy as a single chip.

A Real Part: ADC12DJ4000RF

It exists. The TI ADC12DJ4000RF is a 12-bit RF-sampling ADC with two channels at 4 GSPS, which can be interleaved into a single channel at 8 GSPS. Its analog input bandwidth (−3 dB) is listed as 8 GHz, so a 3.9 GHz tone isn't even close to its limit.

So the short answer to the title is yes: an ADC can sample 3.9 GHz directly. A VNA needs three receivers (the reference channel plus port 1 and port 2), so we would need three of them, just like LibreVNA uses three ADCs.

It's worth knowing that sample rate is not the only route. The analog bandwidth of an ADC can be much higher than half its sample rate, and RF-sampling ADCs deliberately take advantage of aliasing ("undersampling") to capture a band that sits above Nyquist. That relaxes the sample rate, but you still need an ADC whose front end, clock and data path all work at gigahertz frequencies, so most of the problems below remain.

So Why Not Just Do That?

If such an ADC exists, why does almost every VNA, LibreVNA included, still use a heterodyne receiver? Because the ADC is the easy part. Everything around it gets hard:

Start with the clock. Unlike a microcontroller ADC, these converters don't run from an internal timebase: the sample rate is whatever clock you feed into them. Even a modest pipeline ADC like the 14-bit THS1408 has a dedicated CLK pin, and its datasheet specifies the clock frequency range rather than a sample rate setting:

THS1408 recommended operating conditions table, with the clock frequency fCLK from 0.1 to 8 MHz for the THS1408 THS1408 terminal functions table showing the CLK clock input on pin 32
The clock input sets the sample rate: recommended operating conditions and terminal functions. From the TI THS1408 datasheet.
Aspect What it means at 3.9 GHz
Sample clock These ADCs have no internal timebase: you supply the sample clock, and its jitter sets the SNR. At 3.9 GHz, 100 fs of jitter alone limits the SNR to about 52 dB. Reaching the ~74 dB a 12-bit converter could ideally deliver would take under 10 fs.
Data interface Forget SPI. 8 GSPS × 12 bits is about 96 Gb/s per ADC, nearly 300 Gb/s for three, streamed over JESD204C lanes running at up to 17.16 Gb/s each. You need an FPGA with high-speed transceivers just to receive it. SPI is still there, but only to configure registers.
ADC architecture Instead of the familiar SAR or delta-sigma (Δ-Σ) converters, these parts use pipeline, folding-interpolating and time-interleaved architectures, which bring their own calibration and interleaving spurs.
Package and layout Fine-pitch BGA packages, controlled-impedance differential inputs and multi-gigabit routing. Not impossible in a workshop, but the odds of getting it wrong go up fast.
Cost and power The ADCs, the clock and the transceiver-class FPGA together cost far more than the rest of an open-hardware VNA, and their power budget is counted in watts, not milliwatts.
Firmware A sweep from 100 kHz to 6 GHz would push you toward changing the sample rate along the sweep. It is much simpler to keep one fixed sample rate for every point.

The architecture changes the interface too. A pipeline ADC like the 12-bit ADS804 delivers each result on parallel output pins, one per bit, and with latency: the sample taken now shows up several clock cycles later. That's manageable at 10 MSPS; scale it to GSPS and you get the serialized JESD204 lanes described above.

ADS804 timing diagram: the analog input is sampled on each clock edge and data appears on the outputs six clock cycles later ADS804 pin table listing the over-range indicator, the twelve parallel data bits B1 to B12 and the CLK convert clock input
Six clock cycles of pipeline delay and twelve parallel data pins. From the TI ADS804 datasheet.

There's also a deeper mismatch. A VNA measures one frequency at a time. At each sweep point, the only thing it needs is the amplitude and phase of a single, known tone. Capturing 4 GHz of instantaneous bandwidth to then throw away everything but one frequency bin is a lot of hardware spent on nothing.

Bottom line: an ADC can reach 3.9 GHz, but direct sampling turns a VNA project into a high-speed digital and clocking project. For a single-tone measurement, that's the wrong trade.

Option 2: Move the Signal Down First

This problem is not new. Radio engineers ran into it a century ago, and the answer, Edwin Armstrong's superheterodyne receiver from 1918, is still in almost every radio and VNA today. A mixer multiplies the incoming signal with a local oscillator (LO). The output contains the difference frequency, the intermediate frequency (IF), and it keeps the amplitude and phase of the original signal.

The key trick: the LO moves together with the stimulus, so the IF stays at the same frequency for every point of the sweep. The ADC, its anti-alias filter and the digital processing are designed once, for one fixed frequency, no matter whether the stimulus is at 10 MHz or 6 GHz.

The LibreVNA Receiver

LibreVNA uses two conversion stages per receiver, and repeats the chain three times (reference, port 1, port 2). From its KiCad BOM:

Stage Part (×3) What it does
1st mixer ADL5801 Mixes the RF with LO1 down to IF1 = 62 MHz
2nd mixer LT5560 Mixes IF1 with a fixed LO2 of 61.75 MHz down to IF2 = 250 kHz
ADC driver THS4521 Fully differential amplifier that drives the ADC input
ADC MCP33131D-10 16-bit, 1 MSPS SAR ADC, run at 800 kSps
Processing XC6SLX9 (one) Spartan-6 FPGA that reads all three ADCs and computes the DFT at the IF

Compare the data rates: 16 bits × 800 kSps = 12.8 Mb/s per ADC, which a small FPGA reads over a plain serial interface. That's about 7500 times less than the direct-sampling option.

The ADC driver is not decoration either. The MCP33131 datasheet says the input must settle to within ½ LSB during the acquisition time, and that settling depends on the source impedance. Its recommendation is to isolate the ADC from a high-impedance source with a low-noise driver, which is exactly the THS4521's job.

The Numbers in the Firmware

All of these frequencies are constants in the LibreVNA firmware:

jankae/LibreVNA/Software/VNA_embedded/Application/Hardware.hpp Lines 37 to 45 in c477819
static constexpr uint32_t DefaultADCSamplerate = 800000;
static constexpr uint32_t DefaultIF1 = 62000000;
static constexpr uint32_t DefaultIF2 = 250000;
static constexpr uint32_t LO1_minFreq = 25000000;
static constexpr uint32_t MaxSamples = 130944;
static constexpr uint32_t MinSamples = 16;
static constexpr uint32_t PLLRef = 100000000;
static constexpr uint32_t BandSwitchFrequency = 25000000;
static constexpr uint32_t DefaultLO2 = DefaultIF1 - DefaultIF2;

A few things fall out of these lines:

  • The ADC samples the 250 kHz IF at 800 kSps, 3.2 samples per period, comfortably above Nyquist.
  • The minimum is 16 samples. At 800 kSps that's 20 µs, exactly 5 periods of the 250 kHz IF, so the DFT always sees a whole number of cycles.
  • The sample count sets the IF bandwidth. The firmware derives the widest IF bandwidth as 800 kSps / 16 = 50 kHz (fast but noisy), and the narrowest as 800 kSps / 130944 ≈ 6 Hz (slow but with a very low noise floor). This is the "IF bandwidth" setting you trade against sweep time in the GUI.
  • LO2 is fixed at IF1 − IF2 = 61.75 MHz, so only LO1 has to track the sweep.

How Fast Are the ADCs We Already Know?

Once the signal is at a few hundred kilohertz, the ADC requirements drop to the range most of us already work with. It's a good moment to check how far the converters inside common microcontrollers actually go.

Acquisition and Conversion Time

A SAR ADC spends each sample in two phases. The acquisition time is when the input charges the sampling capacitor, and you usually control it. The conversion time is when the SAR logic resolves the bits, and it is fixed by the design. On the MCP33131, for example, a conversion starts on the rising edge of CNVST; when it finishes, the result is clocked out over SPI while the device is already acquiring the next sample. The maximum sample rate is roughly one over the sum of both phases.

MCP33131 timing diagram showing CNVST, SCLK, SDO and the ADC state alternating between input acquisition and conversion
One conversion cycle: acquisition, conversion on the rising edge of CNVST, then data out on SDO while the next acquisition runs. From the Microchip MCP33131 datasheet.

nRF52 and STM32G4

ADC Timing Maximum sample rate
nRF52805/832/840 SAADC Acquisition ≥ 3 µs, conversion < 2 µs ≈ 200 kSps
STM32G4, 12-bit 2.5 + 12.5 cycles at a 60 MHz ADC clock 4 MSPS
STM32G4, 6-bit 2.5 + 6.5 cycles at a 60 MHz ADC clock ≈ 6.7 MSPS
MCP33131D-10 (LibreVNA) 16-bit SAR 1 MSPS, used at 800 kSps

On the nRF52, 3 µs + 2 µs is 5 µs per sample, which is where 200 kSps comes from. It also explains the SAADC's SAMPLERATE register: the sample rate is 16 MHz divided by its CC field, and that field only starts at 80, because 16 MHz / 80 = 200 kHz is the fastest the conversion time allows.

nRF52 SAADC timing table: acquisition time 20 µs for source resistance up to 400 kΩ, 40 µs up to 800 kΩ, conversion time under 2 µs nRF52 SAADC SAMPLERATE register: CC field with a range of 80 to 2047, sample rate is 16 MHz divided by CC
SAADC acquisition and conversion times, and the SAMPLERATE register whose CC field starts at 80. From the Nordic nRF52 product specification.

The STM32G4 is a common trap. My first calculation used the 170 MHz system clock: 9 cycles at 170 MHz gives 18.9 MSPS, which looked suspiciously high, and it is. The ADC kernel clock is limited to 60 MHz (52 MHz when several ADCs run together), as stated in ST's AN5346. With 60 MHz, the real numbers are 4 MSPS at 12 bits and about 6.7 MSPS at 6 bits.

The reference manual explains where the confusion comes from: the ADC clock is selected by software from either the system clock (SYSCLK) or the PLL "P" output, and the conversion time is counted in cycles of that ADC clock, sampling time plus successive-approximation time:

Part of the STM32G4 clock tree showing the PLL outputs and SYSCLK routed to the ADC clock
The ADC clock comes from SYSCLK or PLL "P". From the STM32G4 reference manual.
STM32G4 ADC block diagram with the SMPx sampling time setting circled STM32G4 ADC timing: TCONV equals TSMPL plus TSAR, for example 2.5 plus 12.5 cycles at 12 bits
The SMPx sampling time setting in the ADC block, and the conversion time formula TCONV = TSMPL + TSAR. From the STM32G4 reference manual.

Either way, all of these converters live in the kilohertz-to-megahertz range, a factor of a thousand or more below the 7.8 GSPS the direct approach needs. The heterodyne receiver is what closes that gap.

Verdict

Can an ADC sample 3.9 GHz? Yes. A part like the ADC12DJ4000RF reaches 8 GSPS with 8 GHz of input bandwidth. Should a VNA like LibreVNA do it? No. A femtosecond-class clock, hundreds of gigabits per second of data, BGA packages and a transceiver-class FPGA are a heavy price for measuring one tone at a time. Two mixers move the signal to a fixed 250 kHz IF, and from there a 16-bit SAR ADC and a small Spartan-6 do the rest, with more resolution than the fast converter offers.

In the next part of the series, we'll follow the IF into the FPGA and see how those 16 samples turn into a magnitude and a phase.

Design Takeaways

  1. Start from Nyquist, but don't stop there. Clock jitter, data rate and layout decide whether direct sampling is practical.
  2. Match the receiver to the measurement. A swept, single-tone instrument doesn't need gigahertz of instantaneous bandwidth.
  3. Use a fixed IF. It lets the ADC, its filter and the DSP be designed once for the whole sweep.
  4. Drive SAR ADCs properly. The input must settle within the acquisition time; a low-impedance driver makes that possible.
  5. Check which clock really feeds the ADC before computing a sample rate from the datasheet.